The present invention relates generally to semiconductor integrated circuits and, more particularly, to fabrication of a non-volatile memory with a floating gate.
Non volatile memories having floating gates are widely implemented on integrated circuits. Flash memory (Flash) is one form of a nonvolatile memory having a floating gate and will be referred to for illustrative purposes throughout this specification. Nevertheless, the present invention is not limited to flash memory cells and can be embodied in any alternate form of non-volatile memory cell having a floating gate.
Flash cells can be electrically programmed, erased, and reprogrammed. One technique of implementing Flash is by use of a floating gate tunneling oxide (FLOTOX) transistor. To create a FLOTOX transistor, a field-effect transistor (FET) having source, drain, substrate, and gate terminals is modified to electrically isolate (float) the gate. This polycrystalline silicon (polysilicon) floating gate is created over a thin insulating layer of silicon dioxide (gate oxide). A second polysilicon gate (control gate) is created above the floating gate. The floating gate and control gate are separated by an interpoly insulating layer.
Since the floating gate is electrically isolated, any charge stored on the floating gate is trapped. Storing sufficient charge on the floating gate will create an inversion channel between source and drain of the FET. Thus, the presence or absence of charge on the floating gate represents two distinct data states.
Typically, FLOTOX transistors are selectively programmed by hot electron injection which places a charge on a floating gate during a write. The FLOTOX transistors are selectively erased by Fowler-Nordheim tunneling which removes the a charge from the floating gate. During a write, a high programming voltage is placed on the control gate. This forces an inversion region to form in the p-type substrate. The drain voltage is increased to approximately half the control gate voltage (6 volts) while the source is grounded (0 volts), increasing the voltage drop between the drain and source. In the presence of the inversion region, the current between the drain and source increases. The resulting high electron flow from source to drain increases the kinetic energy of the electrons. This causes the electrons to gain enough energy to overcome the outside barrier and collect on the floating gate.
After the write is completed, the negative charge on the floating gate raises the cell""s threshold voltage (VT) above the wordline logic 1 voltage. When a written cell""s wordline is brought to a logic 1 during a read, the cell will not turn on. Sense amps detect and amplify the cell current, and output a 0 for a written cell.
The floating gate can be erased by grounding the control gate and raising the source voltage to a sufficiently high positive voltage to transfer electrons out of the floating gate to the source terminal of the transistor by tunneling through the insulating gate oxide. After the erase is completed, the lack of charge on the floating gate lowers the cell""s VT below the wordline logic 1 voltage. Thus when an erased cell""s wordline is brought to a logic 1 during a read, the transistor will turn on and conduct more current than a written cell. Some flash devices use Fowler-Nordheim tunneling for writes as well as erase.
The transistors can be selectively reprogrammed in the same manner as described above, since the Fowler-Nordheim tunneling process is nondestructive. The programming and erasure voltages which effect Fowler-Nordheim tunneling are higher than the voltages normally used in reading the memory. Thus the Fowler-Nordheim tunneling effect is negligible at the lower voltages used in reading the memory, allowing a FLOTOX transistor to maintain its programmed state for years if subjected only to normal read cycles.
These contact-less cells typically require approximately a 12 Volt or higher programming voltage. It would be desirable in future uses of Flash memories to lower the programming voltage (and, therefore, lower the power dissipation) while at the same time increasing Flash cell density.
Flash memory cells typically include a capacitor plate which must be fabricated with a large enough area to retain a charge sufficient to withstand the effects of parasitic capacitances and noise due to circuit operation. A major design goal is to minimize the area of a cell to allow cells to be more densely packed on an integrated circuit die. While achieving this goal of increasing cell array density, however, the sufficient capacitance levels of the storage capacitors must be maintained. To date, smaller cell designs necessitate increasing programming voltages in order to maintain required capacitance levels. Increasing the programming voltage, however, increases power dissipation and future flash memories will require lower power dissipation.
xe2x80x9cStacked storage cellxe2x80x9d design""s increase cell density without reducing capacitance by employing capacitive coupling. In this technique, two or more capacitor conductive plate layers, such as polycrystalline silicon (polysilicon or poly), are deposited over a memory cell access transistor on a semiconductor wafer. A high dielectric constant material is sandwiched between these capacitor plate layers. Such a capacitor structure is known as a stacked capacitor cell (STC). STC""s offer increased cell density, however, advances in conventional methods of high resolution photolithography and anisotropic etching have resulted in the development of other methods for increasing cell capacitance.
One approach to increasing memory cell capacitance in the dynamic random access memory (DRAM) arena is to build a three dimensional capacitor structure which extends vertically upward over the cell area. For example, the Tseng U.S. Pat. No. 5,192,702 discloses a method of fabricating a STC by first depositing an etch stop layer over the word lines. A thick layer of conductively doped polysilicon is then deposited, masked, and etched to form a hollow cylindrical STC bottom capacitor plate of height determined by the polysilicon thickness.
In another approach in the DRAM technologies, a form is employed to create the STC. For example, in the Dennison et al. U.S. Pat. No. 5,340,765 a thick silicon dioxide (oxide) layer is deposited on the supporting substrate on which access transistors have been created. The oxide is then planarized and buried contact openings to the access transistors are etched through the oxide. The buried contact openings are used as forms for the conformal deposition of a conductively doped polysilicon STC bottom plate layer. However, the forming of the buried contact openings is confined to the area between adjacent word lines, thereby limiting the area available for depositing the conductive bottom plate layer of the STC capacitor. By limiting the conductive bottom plate electrode area, the capacitance of the memory storage capacitor is also limited.
Thus, there is a need in the art of Flash memory design, for memory cell structures that yield higher capacitive coupling ratios. A method is likewise needed to fabricate nonvolatile high density Flash memory cell structures which yield even higher capacitance coupling ratios and in which the method used to fabricate these structures is compatible with other memory fabrication steps.
The present invention provides a system an method for forming a non volatile memory structure on a silicon substrate having an existing topography. A planarized isolation layer is formed on the existing topography of the substrate having a top surface. A portion of the planarized isolation layer is removed to form walls extending from the top surface of the planarized isolation layer to the existing topography of the substrate. A gate oxide region layer is formed on and conforming to the existing topography of the substrate. A conductive bottom plate layer is formed on and conforming to the top surface of the planarized isolation layer, the walls of the isolation layer, and the gate oxide layer. A dielectric layer is formed on and conforming to the conductive bottom plate layer. Then, a conductive top plate layer is formed on and conforming to the dielectric layer.
According to another aspect of the present invention, a method for forming a non volatile memory array on a silicon substrate with an existing topography is provided. The method includes forming a floating gate tunneling oxide transistor (FLOTOX). The FLOTOX has a first and a second source/drain region and a body region. A floating gate is formed as part of the FLOTOX. Forming the floating gate further includes forming a planarized isolation layer on the existing topography of the substrate. The planarized isolation layer has a top surface. The method further includes removing a portion of the planarized isolation layer to form walls which extend from the top surface of the planarized isolation layer to the existing topography of the substrate. A gate oxide region layer is formed on and conforming to the existing topography of the substrate. A floating gate is formed on and to conforms to the top surface of the planarized isolation layer, the walls of the isolation layer, and the gate oxide layer. Forming the floating gate further includes forming a dielectric layer on and conforming to the floating gate. A control gate is formed that to conform to the dielectric layer. A wordline is formed and coupled to the control gate. A bit line is formed and coupled to the second source/drain region. A source line is formed and coupled to the first source/drain region.
According to another aspect of the present invention, a non volatile memory cell structure on a silicon substrate with an existing topography is provided. The non volatile memory cell structure includes a gate oxide region layer on and conforming to the existing topography of the substrate. A planarized isolation layer surrounds the gate oxide region layer having a top surface. An opening extends from the top surface of the planarized isolation layer to the gate oxide region and is defined by the walls interior to the planarized isolation layer. A conductive bottom plate layer is located on and conforming to the top surface of the planarized isolation layer, the interior walls of the planarized isolation layer, and the gate oxide region. A dielectric layer is located on and conforms to the conductive bottom plate layer. A conductive top plate layer is located on and conforms to the dielectric layer.
According to another aspect of the present invention, a non volatile memory cell array structure on a silicon substrate with existing topography is provided. The array includes a number of floating gate tunneling oxide transistors (FLOTOX) located on the substrate""s existing topography. Each FLOTOX includes a first and second source/drain region, a body region, and a gate oxide region layer on and conforming to the body region. There is also a planarized isolation layer surrounds the gate oxide region layer and has a top surface. An opening extends from the top surface of the planarized isolation layer to the gate oxide region and defined by walls interior to the planarized isolation layer. A floating gate is located on and conforms to the top surface of the planarized isolation layer, the walls of the isolation layer, and the gate oxide layer. A dielectric layer is located on and conforms to the floating gate. A control gate is located on and conforms to the dielectric layer. A wordline couples to the control gate of each FLOTOX. A bit line couples to the second source/drain region and a source line couples to the first source/drain region.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.